Электронная библиотека (репозиторий) Томского государственного университета

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Add   Deriving approximate logic circuits for TMR technique
Authors: Matrosova, Anzhela Yu. | Ostanin, Sergey A. | Goshin, G. G.
Source: Russian physics journal. 2022. Vol. 65, № 4. P. 751-760
Type: статьи в журналах
Date: 2022
Description: The Triple-Modular Redundancy (TMR) technique is one of the conventional approaches to provide reliable functioning of logic circuits. When using outsourcing, it is possible to inject a Trojan Circuit ... More
Add   Applying incompletely specified Boolean functions for patch circuit generation
Authors: Matrosova, Anzhela Yu. | Provkin, V.
Source: 2021 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, September 10-13, 2021 : proceedings. [S. l.], 2021. P. 238-241
Type: статьи в сборниках
Date: 2021
Description: We consider combination circuit C and some its nodes that faults are detected on the last stages of circuit fabrication. Besides, injections of Trojan Circuits (TCs) in certain circuit C lines may be ... More
Add   Masking circuit faults and Trojan circuit injections using sat solvers
Authors: Matrosova, Anzhela Yu. | Provkin, V. А. | Tychinskiy, V. Z. | Nikolaeva, Ekaterina A. | Goshin, G. G.
Source: Russian physics journal. 2021. Vol. 63, № 12. P. 2178-2188
Type: статьи в журналах
Date: 2021
Description: Combinational circuit C composed of gates and its sub-circuit with set V of output nodes and set U of input nodes are considered. The set V consists of output nodes of fault gates of the circuit C (on ... More
Add   SAT solvers application of deriving all test pairs detecting robust testable PDFs
Authors: Matrosova, Anzhela Yu. | Andreeva, V. V. | Tychinskiy, V. Z.
Source: 2021 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, September 10-13, 2021 : proceedings. [S. l.], 2021. P. 252-255
Type: статьи в сборниках
Date: 2021
Description: It is known that if we have set of test pairs of neighbor Boolean vectors for robust testable PDF for each path considered in the given circuit, we may derive test sequence for these faults consisting ... More
Add   Masking internal node logical faults and trojan circuits injections with using SAT solvers
Authors: Matrosova, Anzhela Yu. | Provkin, V.
Source: 2020 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR) : THETA 22nd edition, 21st -23rd May, Cluj-Napoca, Romania : proceedings. [S. l.], 2020. P. 3-6
Type: статьи в сборниках
Date: 2020
Description: We consider a combination circuit (the combinational part of a sequential circuit) and some nodes which faults are detected on the last stages of the circuit fabrication. Besides, injections of Trojan ... More
Add   A high performance scan flip-flop design for serial and mixed mode scan test
Authors: Tudu, Jaynarayan | Matrosova, Anzhela Yu. | Singh, Virendra | Ahlawat, Satyadev
Source: IEEE transactions on device and materials reliability. 2018. Vol. 18, № 2. P. 321-331
Type: статьи в журналах
Date: 2018
Description: Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, ther ... More
Add   Multiple stuck-at fault testability analysis of ROBDD based combinational circuit design
Authors: Matrosova, Anzhela Yu. | Fujita, Masahiro | Singh, Virendra | Shah, Toral
Source: Journal of electronic testing. 2018. Vol. 34, № 1. P. 53-65
Type: статьи в журналах
Date: 2018
Description: Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults sinc ... More
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