Электронная библиотека (репозиторий) Томского государственного университета
Singh, Virendra

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Add   A high performance scan flip-flop design for serial and mixed mode scan test
Authors: Tudu, Jaynarayan | Matrosova, Anzhela Yu. | Singh, Virendra | Ahlawat, Satyadev
Source: IEEE transactions on device and materials reliability. 2018. Vol. 18, № 2. P. 321-331
Type: статьи в журналах
Date: 2018
Description: Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, ther ... More
Add   Multiple stuck-at fault testability analysis of ROBDD based combinational circuit design
Authors: Matrosova, Anzhela Yu. | Fujita, Masahiro | Singh, Virendra | Shah, Toral
Source: Journal of electronic testing. 2018. Vol. 34, № 1. P. 53-65
Type: статьи в журналах
Date: 2018
Description: Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults sinc ... More
Add   A high performance scan flip-flop design for serial and mixed mode scan test
Authors: Ahlawat, Satyadev | Matrosova, Anjela Yu. | Singh, Virendra | Tudu, Jaynarayan
Source: 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 4-6 July 2016, Hotel Eden Roc, Sant Feliu de Guixols, Catalunya, Spain. [S. l.], 2016. P. 233-238
Type: статьи в сборниках
Date: 2016
Add   ROBDD based path delay fault testable combinational circuit synthesis
Authors: Shah, Toral | Singh, Virendra | Matrosova, Anjela Yu.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, October 14-17, 2016. [S. l.], 2016. P. 181-184
Type: статьи в сборниках
Date: 2016
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