Электронная библиотека (репозиторий) Томского государственного университета
Andreeva, V. V.

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Add   SAT solvers application of deriving all test pairs detecting robust testable PDFs
Authors: Matrosova, Anzhela Yu. | Andreeva, V. V. | Tychinskiy, V. Z.
Source: 2021 IEEE East-West Design & Test Symposium (EWDTS), Batumi, Georgia, September 10-13, 2021 : proceedings. [S. l.], 2021. P. 252-255
Type: статьи в сборниках
Date: 2021
Description: It is known that if we have set of test pairs of neighbor Boolean vectors for robust testable PDF for each path considered in the given circuit, we may derive test sequence for these faults consisting ... More
Add   Fault-tolerant synchronous FSM network design for path delay faults
Authors: Andreeva, V. V. | Butorina, Natalia B. | Tretyakov, D. | Ostanin, Sergey A.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018), Kazan, Russia, September 14-17, 2018. [S. l.], 2018. P. 645-648
Type: статьи в сборниках
Date: 2018
Add   Finding false paths in sequential circuits
Authors: Matrosova, Anjela Yu. | Chernyshov, S. V. | Rozhkova, S. V. | Kudin, D. V. | Andreeva, V. V.
Source: Russian physics journal. 2018. Vol. 60, № 10. P. 1837-1844
Type: статьи в журналах
Date: 2018
Description: Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binar ... More
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