Электронная библиотека (репозиторий) Томского государственного университета
Shah, Toral

Add to Quick Collection   All 4 Results

Showing items 1 - 4 of 4.
  • «
  • ←
  • 1
  • →
  • »
Sort:
 Add All Items to Quick Collection
Add   Multiple stuck-at fault testability analysis of ROBDD based combinational circuit design
Authors: Matrosova, Anzhela Yu. | Fujita, Masahiro | Singh, Virendra | Shah, Toral
Source: Journal of electronic testing. 2018. Vol. 34, № 1. P. 53-65
Type: статьи в журналах
Date: 2018
Description: Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults sinc ... More
Add   Simplification of fully delay testable combinational circuits and finding of pdf test pairs
Authors: Matrosova, Anjela Yu. | Mitrofanov, Evgenii V. | Shah, Toral
Source: Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2017. № 39. P. 85-93
Type: статьи в журналах
Date: 2017
Description: Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-ANDXOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of f ... More
Add   ROBDD based path delay fault testable combinational circuit synthesis
Authors: Shah, Toral | Singh, Virendra | Matrosova, Anjela Yu.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, October 14-17, 2016. [S. l.], 2016. P. 181-184
Type: статьи в сборниках
Date: 2016
Add   Simplification of fully delay testable combinational circuits
Authors: Matrosova, Anjela Yu. | Mitrofanov, Evgenii V. | Shah, Toral
Source: Proceedings of the 21st IEEE International On-Line Testing Symposium Symposium (IOLTS), 6-8 July 2015, Athena Pallas Village, Elia, Halkidiki, Greece. [S. l.], 2015. P. 44-45
Type: статьи в сборниках
Date: 2015
  • «
  • ←
  • 1
  • →
  • »
^