https://vital.lib.tsu.ru/vital/access/manager/Index ${session.getAttribute("locale")} 5 Preventing and masking Trojan Circuits triggering out of working area https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000643966 Wed 28 Nov 2018 15:57:36 KRAT ]]> Exchange interaction and its tuning in magnetic binary chalcogenides https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000486183 Wed 12 Dec 2018 15:16:37 KRAT ]]> Detection and masking of trojan circuits in sequential logic https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000623064 Wed 04 Apr 2018 15:56:58 KRAT ]]> Finding false paths for sequential circuits using operations on ROBDDs https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000662225 Wed 02 Oct 2019 10:56:37 KRAT ]]> Fault-tolerant synchronous FSM network design for path delay faults https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000648587 Tue 19 Feb 2019 11:20:59 KRAT ]]> A fault-tolerant sequential circuit design for stuck-at faults and path delay faults https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000624110 Thu 19 Apr 2018 11:20:27 KRAT ]]> Trojan Circuits masking and debugging of combinational circuits with LUT insertion https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000646055 Thu 10 Jan 2019 09:57:37 KRAT ]]> Detection and masking of Trojan Circuits in sequential logic https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000643965 Mon 18 Mar 2019 14:16:13 KRAT ]]> Deriving approximate logic circuits for TMR technique https://vital.lib.tsu.ru/vital/access/manager/Repository/koha:001015290 Mon 11 Dec 2023 14:42:29 KRAT ]]> Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB implementation of Incompletely Specified Boolean Function of the Corresponding Sub-circuit https://vital.lib.tsu.ru/vital/access/manager/Repository/vtls:000520576 Mon 01 Jul 2019 12:44:37 KRAT ]]>