Электронная библиотека (репозиторий) Томского государственного университета
статьи в сборниках | Ostanin, Sergey A.

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Add   Fault-tolerant synchronous FSM network design for path delay faults
Authors: Andreeva, V. V. | Butorina, Natalia B. | Tretyakov, D. | Ostanin, Sergey A.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018), Kazan, Russia, September 14-17, 2018. [S. l.], 2018. P. 645-648
Type: статьи в сборниках
Date: 2018
Add   Finding false paths for sequential circuits using operations on ROBDDs
Authors: Matrosova, Anjela Yu. | Ostanin, Sergey A. | Chernyshov, Semen V.
Source: 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS 2018), 2-4 July 2018, Spain. [S. l.], 2018. P. 240-242
Type: статьи в сборниках
Date: 2018
Description: Performance of VLSI is, first of all, its high operation
Add   Trojan Circuits masking and debugging of combinational circuits with LUT insertion
Authors: Matrosova, Anjela Yu. | Ostanin, Sergey A.
Source: 2018 IEEE International conference on automation, quality and testing, robotics (AQTR) : THETA 21st edition, 24th-26th May, Cluj-Napoca, Romania : proceedings. [S. l.], 2018. P. [1-6]
Type: статьи в сборниках
Date: 2018
Description: It is extremely difficult to provide 100% correctness of fabricated high performance circuits. Manufactured circuits may have logical and electrical bugs, Trojan Circuits (TCs) inclusions and so on. S ... More
Add   Detection and masking of Trojan Circuits in sequential logic
Authors: Mitrofanov, Evgenii V. | Ostanin, Sergey A. | Nikolaeva, Ekaterina A. | Matrosova, Anjela Yu.
Source: Proceedings of 2017 IEEE East-West Design & Test Symposium (EWDTS), Novi Sad, Serbia, September 27 – October 2, 2017. [S. l.], 2017. P. 137-140
Type: статьи в сборниках
Date: 2017
Description: A technique of finding a set of sequential circuit
Add   Preventing and masking Trojan Circuits triggering out of working area
Authors: Mitrofanov, Evgenii V. | Ostanin, Sergey A. | Kirienko, Irina E. | Matrosova, Anjela Yu.
Source: 2017 European Conference on Circuit Theory and Design (ECCTD), September 4-6, 2017, Catania, Italy. [S. l.], 2017. P. [1-4]
Type: статьи в сборниках
Date: 2017
Description: Inserting malicious sub-circuits that may cause a
Add   Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB implementation of Incompletely Specified Boolean Function of the Corresponding Sub-circuit
Authors: Matrosova, Anjela Yu. | Ostanin, Sergey A. | Kirienko, Irina E.
Source: Proceedings 2015 IEEE : 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2015), 22-24 April 2015, Belgrade, Serbia. Los Alamitos [et.al.], 2015. P. 267-270
Type: статьи в сборниках
Date: 2015
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