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Source: Russian physics journal. 2021. Vol. 63, № 12. P. 2178-2188
Type: статьи в журналах
Date: 2021
Description:
Combinational circuit C composed of gates and its sub-circuit with set V of output nodes and set U of input nodes are considered. The set V consists of output nodes of fault gates of the circuit C (on
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Source: IEEE transactions on device and materials reliability. 2018. Vol. 18, № 2. P. 321-331
Type: статьи в журналах
Date: 2018
Description:
Over the years, serial scan design has become the de-facto design for testability technique. The ease of testing and high test coverage has made it gain widespread industrial acceptance. However, ther
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Source: Journal of electronic testing. 2018. Vol. 34, № 1. P. 53-65
Type: статьи в журналах
Date: 2018
Description:
Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults sinc
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