Электронная библиотека (репозиторий) Томского государственного университета
Ostanin, Sergey A.

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Source: Russian physics journal. 2022. Vol. 65, № 4. P. 751-760
Type: статьи в журналах
Date: 2022
Description: The Triple-Modular Redundancy (TMR) technique is one of the conventional approaches to provide reliable functioning of logic circuits. When using outsourcing, it is possible to inject a Trojan Circuit ... More
Source: Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2018. № 42. С. 89-99
Type: статьи в журналах
Date: 2018
Description: Inserting malicious sub-circuits that may destroy a logical circuit or provide leakage of confidential information from a system containing the logical circuit demands detection of such sub-circuits f ... More
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018), Kazan, Russia, September 14-17, 2018. [S. l.], 2018. P. 645-648
Type: статьи в сборниках
Date: 2018
Source: 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS 2018), 2-4 July 2018, Spain. [S. l.], 2018. P. 240-242
Type: статьи в сборниках
Date: 2018
Description: Performance of VLSI is, first of all, its high operation
Source: 2018 IEEE International conference on automation, quality and testing, robotics (AQTR) : THETA 21st edition, 24th-26th May, Cluj-Napoca, Romania : proceedings. [S. l.], 2018. P. [1-6]
Type: статьи в сборниках
Date: 2018
Description: It is extremely difficult to provide 100% correctness of fabricated high performance circuits. Manufactured circuits may have logical and electrical bugs, Trojan Circuits (TCs) inclusions and so on. S ... More
Source: Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2017. № 41. С. 61-68
Type: статьи в журналах
Date: 2017
Description: This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has only one self-checking sequential circuit, normal (unprotecte ... More
Source: Proceedings of 2017 IEEE East-West Design & Test Symposium (EWDTS), Novi Sad, Serbia, September 27 – October 2, 2017. [S. l.], 2017. P. 137-140
Type: статьи в сборниках
Date: 2017
Description: A technique of finding a set of sequential circuit
Source: 2017 European Conference on Circuit Theory and Design (ECCTD), September 4-6, 2017, Catania, Italy. [S. l.], 2017. P. [1-4]
Type: статьи в сборниках
Date: 2017
Description: Inserting malicious sub-circuits that may cause a
Source: Proceedings 2015 IEEE : 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS 2015), 22-24 April 2015, Belgrade, Serbia. Los Alamitos [et.al.], 2015. P. 267-270
Type: статьи в сборниках
Date: 2015
Source: Physical Review B. 2014. Vol. 89, Issue 16. P. 165202-1-165202-7
Type: статьи в журналах
Date: 2014
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