Электронная библиотека (репозиторий) Томского государственного университета
Matrosova, Anjela Yu.

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Add   Detection and masking of trojan circuits in sequential logic
Authors: Matrosova, Anjela Yu. | Ostanin, Sergey A. | Butorina, Nataly Borisovna | Pahomova, Elena Grigorievna | Shulga, Sergey Anatolievich | Mitrofanov, Evgenii V.
Source: Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2018. № 42. С. 89-99
Type: статьи в журналах
Date: 2018
Description: Inserting malicious sub-circuits that may destroy a logical circuit or provide leakage of confidential information from a system containing the logical circuit demands detection of such sub-circuits f ... More
Add   Finding false paths for sequential circuits using operations on ROBDDs
Authors: Matrosova, Anjela Yu. | Ostanin, Sergey A. | Chernyshov, Semen V.
Source: 2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design (IOLTS 2018), 2-4 July 2018, Spain. [S. l.], 2018. P. 240-242
Type: статьи в сборниках
Date: 2018
Description: Performance of VLSI is, first of all, its high operation
Add   Finding false paths in sequential circuits
Authors: Matrosova, Anjela Yu. | Chernyshov, S. V. | Rozhkova, S. V. | Kudin, D. V. | Andreeva, V. V.
Source: Russian physics journal. 2018. Vol. 60, № 10. P. 1837-1844
Type: статьи в журналах
Date: 2018
Description: Method of finding false paths in sequential circuits is developed. In contrast with heuristic approaches currently used abroad, the precise method based on applying operations on Reduced Ordered Binar ... More
Add   Forming patch functions and combinational circuit rectification
Authors: Chernyshov, S. V. | Goshin, G. | Kudin, D. V. | Matrosova, Anjela Yu.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2018), Kazan, Russia, September 14-17, 2018. [S. l.], 2018. P. 726-730
Type: статьи в сборниках
Date: 2018
Description: Increasing chips complexity originates a problem of
Add   Trojan Circuits masking and debugging of combinational circuits with LUT insertion
Authors: Matrosova, Anjela Yu. | Ostanin, Sergey A.
Source: 2018 IEEE International conference on automation, quality and testing, robotics (AQTR) : THETA 21st edition, 24th-26th May, Cluj-Napoca, Romania : proceedings. [S. l.], 2018. P. [1-6]
Type: статьи в сборниках
Date: 2018
Description: It is extremely difficult to provide 100% correctness of fabricated high performance circuits. Manufactured circuits may have logical and electrical bugs, Trojan Circuits (TCs) inclusions and so on. S ... More
Add   A fault-tolerant sequential circuit design for stuck-at faults and path delay faults
Authors: Matrosova, Anjela Yu. | Kirienko, Irina E. | Nikolaeva, Ekaterina A. | Ostanin, Sergey A.
Source: Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2017. № 41. С. 61-68
Type: статьи в журналах
Date: 2017
Description: This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has only one self-checking sequential circuit, normal (unprotecte ... More
Add   Detection and masking of Trojan Circuits in sequential logic
Authors: Mitrofanov, Evgenii V. | Ostanin, Sergey A. | Nikolaeva, Ekaterina A. | Matrosova, Anjela Yu.
Source: Proceedings of 2017 IEEE East-West Design & Test Symposium (EWDTS), Novi Sad, Serbia, September 27 – October 2, 2017. [S. l.], 2017. P. 137-140
Type: статьи в сборниках
Date: 2017
Description: A technique of finding a set of sequential circuit
Add   Preventing and masking Trojan Circuits triggering out of working area
Authors: Mitrofanov, Evgenii V. | Ostanin, Sergey A. | Kirienko, Irina E. | Matrosova, Anjela Yu.
Source: 2017 European Conference on Circuit Theory and Design (ECCTD), September 4-6, 2017, Catania, Italy. [S. l.], 2017. P. [1-4]
Type: статьи в сборниках
Date: 2017
Description: Inserting malicious sub-circuits that may cause a
Add   Simplification of fully delay testable combinational circuits and finding of pdf test pairs
Authors: Matrosova, Anjela Yu. | Mitrofanov, Evgenii V. | Shah, Toral
Source: Вестник Томского государственного университета. Управление, вычислительная техника и информатика. 2017. № 39. P. 85-93
Type: статьи в журналах
Date: 2017
Description: Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-ANDXOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of f ... More
Add   A fault-tolerant sequential circuit design for SAFs and PDFs soft errors
Authors: Matrosova, Anjela Yu. | Kirienko, I. E. | Nikolaeva, E. A. | Ostanin, S. A.
Source: 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 4-6 July 2016, Hotel Eden Roc, Sant Feliu de Guixols, Catalunya, Spain. [S. l.], 2016. P. [1-2]
Type: статьи в сборниках
Date: 2016
Add   A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit
Authors: Ostanin, S. A. | Butorina, Natalia Borisovna | Lavrov, V. A. | Matrosova, Anjela Yu.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, October 14-17, 2016. [S. l.], 2016. P. 607-610
Type: статьи в сборниках
Date: 2016
Add   A high performance scan flip-flop design for serial and mixed mode scan test
Authors: Ahlawat, Satyadev | Matrosova, Anjela Yu. | Singh, Virendra | Tudu, Jaynarayan
Source: 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), 4-6 July 2016, Hotel Eden Roc, Sant Feliu de Guixols, Catalunya, Spain. [S. l.], 2016. P. 233-238
Type: статьи в сборниках
Date: 2016
Add   Patching circuit design based on reserved CLBs
Authors: Matrosova, Anjela Yu. | Ostanin, S. A. | Andreeva, V.
Source: 2016 IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR), 19th - 21st May, Cluj-Napoca, Romania : proceedings. [S. l.], 2016. P. [1-5]
Type: статьи в сборниках
Date: 2016
Add   Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults
Authors: Matrosova, Anjela Yu. | Mitrofanov, Evgenii V.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, October 14-17, 2016. [S. l.], 2016. P. 533-536
Type: статьи в сборниках
Date: 2016
Add   ROBDD based path delay fault testable combinational circuit synthesis
Authors: Shah, Toral | Singh, Virendra | Matrosova, Anjela Yu.
Source: Proceedings of IEEE East-West Design & Test Symposium (EWDTS'2016), Yerevan, Armenia, October 14-17, 2016. [S. l.], 2016. P. 181-184
Type: статьи в сборниках
Date: 2016
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