A fault-tolerant sequential circuit design for stuck-at faults and path delay faults

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A fault-tolerant sequential circuit design for stuck-at faults and path delay faults	413 KB	Adobe Acrobat PDF	Read	Download
DOI Доступ к ресурсу на сайте издателя			10.17223/19988605/41/8

Title: A fault-tolerant sequential circuit design for stuck-at faults and path delay faults
Title: Проектирование отказоустойчивых последовательностных схем для константных неисправностей и неисправностей задержек путей
Creator: Matrosova, Anjela Yu.
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Kirienko, Irina E.
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Nikolaeva, Ekaterina A.
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Ostanin, Sergey A.
Date: 2017
DOI: 10.17223/19988605/41/8
Description: This paper presents a fault-tolerant synchronous sequential circuit design based on self-checking system with low overhead. The scheme has only one self-checking sequential circuit, normal (unprotected) sequential circuit and not selftesting checker. It is proved the reliability properties of the suggested scheme both for single stuck-at faults (SAFs) at gate poles and path delay faults (PDFs), transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared. Estimations of the schemes complexity are discussed.